GaN class E/F transmitter test board

Photo of assembled board

Assembled PCB (tiny silver squares are the GaN devices)

I designed this board a couple of years ago to try a very simple class E/F transmitter, after being introduced to the topology by K6JCA in a blog post about his 80-m class-E/F amplifier project. Class E/F is a zero-voltage switching (ZVS) topology similar in many ways to the better known (in amateur circles anyway) class-E amplifier, but with a lower peak drain voltage for a given output power, and lower peak-to-average drain current ratio (current waveform closer to square). See K6JCA's blog posts and the paper by Kee et al., The class-E/F family of ZVS switching amplifiers. I used the same variant as K6JCA, a push-pull circuit with a resonant tank between the drains, which the paper terms "class E/F_odd" because the tank acts as a differential short circuit at all odd harmonics.

One of my long-term goals is to experiment with high-efficiency "polar transmit" architectures. In these designs, the modulation is split into amplitude and phase components (rather than the usual in-phase and quadrature). The carrier is phase modulated, then sent to a high-efficiency, nonlinear amplifier. The amplitude modulation is applied at the amplifier supply voltage terminal (generally the drain of a FET, hence "drain modulation"). When implemented as an amplifier (analog in, analog out), this is sometimes called the "envelope elimination and restoration" (EER) or Kahn technique. When implemented as a transmitter, an FPGA generates both the phase-modulated carrier and amplitude modulation. In both cases, the amplitude modulator requires a DC-DC switching power supply; otherwise, the power which would have been wasted as heat in a linear RF amplifier will simply be wasted in the linear modulator instead.

Circuit design

Test board schematic

This circuit is a first baby-step in that direction. I wanted to try using some inexpensive gallium nitride (GaN) FETs which have recently become available. The EPC2037 devices used in this project cost about a dollar each and have a typical gate charge of only 115 pico-coulombs! In the HF bands they can be driven directly from fast 5V logic. The only drawback from a hobbyist's point of view is their chip-scale package, essentially a tiny BGA, less than 1 mm square, with 0.45-mm ball pitch. This packaging is actually important for reducing parasitic inductance in their intended applications, and although not easy to solder, isn't as bad as you might guess; there are only four pads after all! I found hot-air soldering was most successful with a very thin layer of tacky flux (Chip Quick SMD291NL) and plenty of bottom pre-heat. (The EPC web site has a video showing the recommended re-work procedure.) Large copper areas connected to the FETs can make soldering difficult, but they are important for heat dissipation during operation.

Here is a close-up of the GaN FETs and "gate drivers" (single UHS logic gates). The FETs are about as wide as the blue-colored 0603 passives:

Test board close-up Test board layout

Following K6JCA's design procedure, I selected values for the tank circuit, aiming for operation at 13.56 MHz. The circuit was then simulated and fine-tuned in LTSpice using EPC-provided models for the EPC2037, and ideal switches with series resistance for the gate drive. I wound the air-core transformer on a section of bubble-tea plastic straw with the primary and secondary windings as close together as possible to maximize coupling. I used an online inductance calculator but did not measure the built coil; the inductance may have been off because the best operating frequency ended up closer to 10.8 MHz! This was not a problem for the purpose of the experiment.

The GaN FETs Q1 and Q2 are driven by single UHS logic gates running at 5V. I made the mistake of not equalizing propagation delay between the two FETs. One of the gates effectively has an extra inverter in it, so the output contained some 2nd harmonic which normally would be suppressed by the balanced push-pull topology.

The PCB was designed on OSH Park's four-layer process, with large copper areas and no thermal reliefs on the FET source and drain terminals. This maximizes thermal performance and minimizes parasitic inductance. The gate connections were made as short and fat as reasonably practical, again to reduce parasitic inductance. (GaN FETs have a very small range from minimum Vgs_on, about 4.5V, to absolute max Vgs, about 6V, so it is vitally important to prevent gate ringing.) In the layout (screen capture above), the GaN FET pads are barely visible as a square of tiny purple dots (openings in the solder mask), pointed to by the white arrows. Another benefit of the large copper fills is that the solder-mask-defined pads for the FETs can be mis-registered slightly, without ruining the footprint.


The circuit was powered with separate 5V and VDD lab supplies and the input square wave was provided by my function generator. A non-inductive, 50-ohm power resistor with a small heatsink was connected to the output for testing.

At the time of construction, my only means for measuring output power were the cursors on my oscilloscope. With some harmonic content in the output, this was not very accurate, but I believe the drain efficiency was well over 90%. With the drain supply at 15V, 0.96A DC input current, and no heat sink on the FETs, about 14W output power was achieved. The output amplitude is quite linear with drain voltage.